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Renesas Electronics /R7FA6M3AH /EPTPC0 /SYCIDRL

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Interpret as SYCIDRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SYCIDRL

Description

SYNFP Local Clock ID Registers

Fields

SYCIDRL

These bits hold the setting for the lower-order 32 bits of the clock-ID of your port.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data